Merge

diff --cc tools/libxc/xc_ia64_stubs.c
Simple merge

diff --cc xen/arch/ia64/vmx/vmx_support.c
Simple merge

diff --cc xen/arch/ia64/xen/domain.c
Simple merge

diff --cc xen/include/public/arch-ia64.h
index f3bb61a93219b32bebc40bc88f42a60b74354241,dd555e1c4d9140c3cb68f272c8e3a84eb9db5ae7..01ce7d02d0000e1cbe069f82673860122280b59f
--- 1/xen/include/public/arch-ia64.h
--- 2/xen/include/public/arch-ia64.h
+++ b/xen/include/public/arch-ia64.h
@@@ -20,51 -20,24 +20,51 @@@ typedef struct 
  } mm_section_t;
  
  typedef struct {
-     unsigned long     mfn : 56;
-     unsigned long     type: 8;
+     unsigned long mfn : 56;
+     unsigned long type: 8;
  } pmt_entry_t;
  
- #define GPFN_MEM              (0UL << 56)     /* Guest pfn is normal mem */
- #define GPFN_FRAME_BUFFER     (1UL << 56)     /* VGA framebuffer */
- #define GPFN_LOW_MMIO         (2UL << 56)     /* Low MMIO range */
- #define GPFN_PIB              (3UL << 56)     /* PIB base */
- #define GPFN_IOSAPIC          (4UL << 56)     /* IOSAPIC base */
- #define GPFN_LEGACY_IO                (5UL << 56)     /* Legacy I/O base */
- #define GPFN_GFW              (6UL << 56)     /* Guest Firmware */
- #define GPFN_HIGH_MMIO                (7UL << 56)     /* High MMIO range */
+ #define GPFN_MEM          (0UL << 56) /* Guest pfn is normal mem */
+ #define GPFN_FRAME_BUFFER (1UL << 56) /* VGA framebuffer */
+ #define GPFN_LOW_MMIO     (2UL << 56) /* Low MMIO range */
+ #define GPFN_PIB          (3UL << 56) /* PIB base */
+ #define GPFN_IOSAPIC      (4UL << 56) /* IOSAPIC base */
+ #define GPFN_LEGACY_IO    (5UL << 56) /* Legacy I/O base */
+ #define GPFN_GFW          (6UL << 56) /* Guest Firmware */
+ #define GPFN_HIGH_MMIO    (7UL << 56) /* High MMIO range */
  
- #define GPFN_IO_MASK          (7UL << 56)     /* Guest pfn is I/O type */
- #define GPFN_INV_MASK         (31UL << 59)    /* Guest pfn is invalid */
+ #define GPFN_IO_MASK     (7UL << 56)  /* Guest pfn is I/O type */
+ #define GPFN_INV_MASK    (31UL << 59) /* Guest pfn is invalid */
  
- #define INVALID_MFN              (~0UL)
+ #define INVALID_MFN       (~0UL)
  
 +#define MEM_G   (1UL << 30)   
 +#define MEM_M   (1UL << 20)   
 +
 +#define MMIO_START       (3 * MEM_G)
 +#define MMIO_SIZE        (512 * MEM_M)
 +
 +#define VGA_IO_START     0xA0000UL
 +#define VGA_IO_SIZE      0x20000
 +
 +#define LEGACY_IO_START  (MMIO_START + MMIO_SIZE)
 +#define LEGACY_IO_SIZE   (64*MEM_M)  
 +
 +#define IO_PAGE_START (LEGACY_IO_START + LEGACY_IO_SIZE)
 +#define IO_PAGE_SIZE  PAGE_SIZE
 +
 +#define STORE_PAGE_START (IO_PAGE_START + IO_PAGE_SIZE)
 +#define STORE_PAGE_SIZE        PAGE_SIZE
 +
 +#define IO_SAPIC_START   0xfec00000UL
 +#define IO_SAPIC_SIZE    0x100000
 +
 +#define PIB_START 0xfee00000UL
 +#define PIB_SIZE 0x100000 
 +
 +#define GFW_START        (4*MEM_G -16*MEM_M)
 +#define GFW_SIZE         (16*MEM_M)
 +
  /*
   * NB. This may become a 64-bit count with no shift. If this happens then the 
   * structure size will still be 8 bytes, so no other alignments will change.